Temperature stable voltage references have been available for a considerable time, particularly in bipolar transistor integrated circuit (IC) form. However, such circuits are not suitable for high density large scale integrated circuit (LSIC) form. In the metal oxide semiconductor (MOS) arts, reference voltages are usually developed by biasing a transistor in their subthreshold region to keep their conduction reasonably low. However, in this mode junction leakage can be a problem. In complementary MOS (CMOS), references have been constructed using the well-known bipolar parasitic transistor structures. These devices represent problems in that they too require substantial areas and their performance is subject to limits imposed by the CMOS devices. They cannot be optimized without upsetting CMOS device properties.